1. Field of the Invention
This invention relates generally to an interactive terminal computing system, and more particularly to a means for generating a nonmaskable interrupt when a central processor unit attempts to write into a memory which is in a write protect mode.
2. Description of the Prior Art
Many computing systems including terminal systems have a number of subsystems coupled to a central processor unit (CPU) which includes a microprocessor. A subsystem desiring to communicate with another subsystem sends a signal to the CPU requesting an interrupt, The CPU processes the interrupt by branching to a particular firmware routine to process the interrupt. A distinct interrupt vector for each subsystem is stored in a memory and points to the starting address of the firmware routine.
Typical systems are described in U.S. Pat. No. 4,240,140 entitled "CRT Terminal Priority Interrupt Apparatus for Generating Vectored Addresses" and in U.S. Pat. No. 4,255,786 entitled "Multi-Way Vectored Interrupt Capability".
The vectored interrupt controls the overall system operation; however, if any of the interrupt vectors stored in memory are changed either deliberately or inadvertently, then the system may "crash".
It should be understood that the references cited herein are those of which the applicants are aware and are presented to acquaint the reader with the level of skill in the art and may not be the closest reference to the invention. No representation is made that any search has been conducted by the applicants.